Control signals must be interchanged between two or more components in many applications, special importance being attached to data integrity during transmission.
In the field of clock-controlled data transmission, it is known practice, in serial data transmission, for example in the CAN or FlexRay protocol, to form checksums over the transmitted data and to transmit said checksums together with the data. At the receiver end, it is thus possible to use the checksums to check the received data. In the case of clocked data transmission, it is generally known practice to form horizontal checksums over data transmitted in succession and to form vertical checksums over data transmitted in a parallel manner at the same time and to transmit said checksums together with the data to a receiver. In this case, for clock-controlled data transmission, it is necessary either to additionally transmit a clock to the receiver or to recover the clock at the receiver using a complicated circuit. Both disadvantageously constitute an outlay which is accepted only for complex systems.